1. Field of the Invention
The disclosure relates to an electron beam (EB) lithography method, more particularly, to an EB lithography method using a new material.
2. Description of the Related Art
An electron beam (EB) lithography process is used to delineate a circuit pattern during the fabrication of a semiconductor integrated circuit (IC). In general, a lithography process includes transferring a mask pattern onto a photoresist; and etching an underlying layer using a pattern of the transferred photoresist. The process of transferring the mask pattern has primarily been performed using light (especially ultraviolet (UV) rays). However, as the integration density and capacity of semiconductor devices increase, techniques of reducing the linewidth of patterns have rapidly been developed. For example, in a UV-photolithography process as a conventional fine processing technique, since the resolution and comformability of patterns are limited to 1 μm and ±3 μm, respectively, it becomes difficult to reduce the linewidth of the patterns to a sufficient degree. Accordingly, a variety of techniques and apparatuses have recently been developed in order to form patterns with a fine linewidth, and thus the advancement of related applications has been accelerated. As a result, not only far infrared (FIR) rays, but also electron beams (e-beams), x-rays, ion beams, and laser beams have been developed and utilized as energy sources.
Also, a conventional EB lithography technique has been used as one of methods for forming patterns with a fine linewidth of 0.1 μm or less. In general, this EB lithography technique includes coating a photoresist on a substrate; partially exposing the photoresist by scanning electron rays at high speed through a predetermined mask layer; and forming a photoresist pattern by performing a developing process. However, the conventional EB lithography technique is reaching the technical limit for forming finer patterns. For example, in the case of 193-nm ArF lithography, the linewidth of patterns is limited to about 45 nm, whereas in the case of SEM lithography, the linewidth of patterns is limited to about 30 nm. Therefore, in order to fabricate a more highly integrated larger-capacity semiconductor device, it is necessary to further reduce the linewidth of patterns using a lithography process.